As noted in U.S. Pat. No. 5,634,119 granted May 27, 1997 entitled "Computer processing unit employing a separate millicode branch history table" described a computer processing system which has memory mapped into at least a first and second region, with the first region storing instructions belonging to a first instruction set architecture of the computer processing system and with the second region storing instructions belonging to a second instruction set architecture of the computer processing system. In such a system a computer processing system included first memory that stores instructions belonging to a first set of instructions and a second memory that stores instructions belonging to a second set of instructions. An instruction buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the instruction buffer according to data stored in a first table. In the second mode, instructions are fetched from the second memory into the instruction buffer according to data stored in a second table. Typically, the first and second set of instructions include at least one branch type instruction. In the illustrative embodiment, each set of instructions had its own Branch History Table (BHT). The first table is a branch history table associated with the first set of instructions and the second table is a branch history table associated with the second set of instructions. The first set of instructions may be system level instructions and the second set of instructions may be millicode instructions that for example, define a complex system level instruction and/or emulate a second instruction set architecture.
The IBM S/390 (both registered trademarks of International Business Machines Corporation) in a feature used in IBM's ESA/390 G4 machines which used millicode in the hierarchical cache structure and a millimode operating mode as well as a system mode using a read only storage structure for millicode in an SMP environment. In a later generation there is a processor that uses a single Branch History Table to hold branch information for all modes of operations. The operation of the branch history table allows the instruction fetch operations in the processor to proceed to the targeted instruction stream without direction first being given as a result of decoded or executing instructions. There are certain actions that millicode performs that requires control over the operation and actions of instruction fetching. These may include types and addresses of requests sent to the cache for functional reasons.
It is noted that many processor designs have available global disable functions to stop BHT operation if there has been a hardware failure or functional problem with the BHT. Those that are skilled in the art would be aware of this existence and use.